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ST3L01
TRIPLE VOLTAGE REGULATOR
s s s s s s
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DUAL INPUT VOLTAGE (12V AND 5V) TRIPLE OUTPUT VOLTAGE (2.6V, 3.3V, 8V) 2.6V GUARANTEED IOUT UP TO 1.2A 3.3V GUARANTEED IOUT UP TO 1.0A 8V GUARANTEED IOUT UP TO 200mA THERMAL AND SHORT CIRCUIT PROTECTION GUARANTEED OPERATING TEMPERATURE RANGE (0C to 125C)
SPAK-7L (PowerFlexTM)
DESCRIPTION This device contains three voltage regulators, all fixed output voltage, in one 7 pin surface mount package. The first is a 2.6 V regulator to power the integrated controller/P. The second is a 3.3V regulator to power the read channel chip, and memory chips requiring 3.3V The last is an 8V regulator to power the preamp chip. The bandgap reference, the 8V ground, and the substrate are all tied to a common ground pin, while the 2.6V and 3.3V ground is tied to a separate ground pin.This
grounding scheme allows for improved noise isolation between the 8V regulator and the 2.6V and 3.3V regulators.The 2.6V and 3.3V regulators shall be respectively capable of 1.0A and 1.2A. The 8V regulator shall be capable of 200mA. It is housed in the SPAK (PowerFlexTM)
SCHEMATIC DIAGRAM
V2.6
March 2002
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ST3L01
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VESD Tstg TJ Supply Voltage ISupply Voltage ESD Tolerance (Human Body Model) Storage Temperature Range Operating Junction Temperature Range Parameter Value 18 18 4 -65 to +150 0 to +150 Unit V V KV C C
GENERAL OPERATING CONDITION
Symbol VCC VCC tr tf VDD VDD tr tf TAl VCC Supply Voltage VCC Ripple Rise Time (10% to 90%) referred to VCC Fall Time (90% to 10%) referred to VCC VDD Supply Voltage VDD Ripple Rise Time (10% to 90%) referred to VDD Fall Time (90% to 10%) referred to VDD Operating Ambient Temperature Range Parameter Value 4.75 to 5.25 0.15 1 1 10.8 to 13.2 0.3 1 1 0 to 70 Unit V V V V V V V V s
THERMAL DATA
Symbol Rthj-case Parameter Thermal Resistance Junction-case SPAK-7L 2 Unit C/W
CONNECTION DIAGRAM (top view)
PIN DESCRIPTION
Pin N Symbol 1 2 3 4 5 VO2 VCC GND3 VO3 VDD VO1 Name and Function Second Output Pin: Bypass with a 0.1F capacitor to GND Input Pin: Bypass with a 0.1F capacitor to GND VO3 regulators GND pin Third Output Pin: Bypass with a 0.1F capacitor to GND Input Pin: Bypass with a 0.1F capacitor to GND First Output Pin: Bypass with a 0.1F capacitor to GND
GND1,2 VO1 and VO2 regulators GND pin
SPAK-7L
6 7
ORDERING INFORMATION
TYPE ST3L01
(*) Available in Tape & Reel with the suffix "R"
SPAK (Power FlexTM) 7 leads (*) ST3L01K7
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ST3L01
TYPICAL APPLICATION CIRCUIT
Note: To improve noise figure of the 8V VREG connect this capacitor to the GND8V pin. CCC, CDD, CO1, CO2 and CO3 capacitors must be located not more than 0.5" from the output pins of the device. Form more details about Capacitors read the "Application Hints"
ELECTRICAL CHARACTERISTICS (VCC=5V, VDD=12V, CCC=1F (Tantalum), C DD=0.1F (X7R), CO1=CO2=C O3=0.11F (X7R) Tj=0 to 125C unless otherwise specified. Typical values are referred at Tj=25C, IFL1 =1.2A, IFL2 =1.0A, IFL3 =0.2A,
Symbol VO1 Parameter Output Voltage 1 IO1 = 10mA IO1 = 0 to IFL1 Tj = 0 to 125C VDD = 0 to 10.8V VO2 Output Voltage 2 IO2 = 10mA IO2 = 0 to IFL2 Tj = 0 to 125C VDD = 0 to 10.8V VO3 Output Voltage 3 IO3 = 10mA IO3 = 0 to IFL3 Tj = 0 to 125C VO VO VD1 VD2 VD3 tTR IOL1 IOL2 IOL3 IO1 IO2 IO3 Line Regulation 1 Load Regulation 1 Dropout Voltage 1 Dropout Voltage 2 Dropout Voltage 3 Transient Response Output 1 Current Limit Output 2 Current Limit Output 3 Current Limit Output 1 Minimum Load Current Output 2 Minimum Load Current Output 3 Minimum Load Current IO = 10mA IO = 0.01 to IFL IO1 = IFL1 IO2 = IFL2 IO3 = IFL3 (Note 3, 7) VO = 125mV VO = 165mV VOUT = 400mV (Note 4, 7) (Note 4, 7) (Note 4, 7) Test Conditions Tj = 25C VCC = 4.75 to 5.25V IO1 = 0.5A Tj = 25C VCC = 4.75 to 5.25V IO2 = 0.5A Tj = 25C VDD = 10.8 to 13.2V VCC =5% (Note 1) (Note 2) (Note 2) (Note 2) 1.5 1.1 0.25 VDD =10% Min. 2.575 2.55 2.2 3.23 3.2 2.92 7.84 7.76 8 8 <0.2 <0.4 1.3 1.13 1.6 <1 2.1 1.7 0.4 2.5 2.5 0.5 0 0 0 1.9 1.4 2.2 3.3 3.3 Typ. 2.6 2.6 Max. 2.626 2.65 2.65 3.37 3.4 3.4 8.16 8.24 %VO %VO V V V s A A A mA mA mA V V Unit V
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ST3L01
Symbol CO CCC CDD SVR1 SVR2 SVR3 IVCC IVDD eN VO VO
Parameter Output Capacitor Input Capacitor Input Capacitor Supply Voltage Rejection (VCC to Output 1) Supply Voltage Rejection (VCC to Output 2) Supply Voltage Rejection (VDD to Output 3) VCC Quiescent Current VDD Quiescent Current Output Noise Temperature Stability Long Term Stability (Note 5, 7) (Note 5) (Note 5)
Test Conditions
Min. 0.1 1.0 0.1
Typ.
Max.
Unit F F F
RegTherm Therma Regulation
IOUT = IFL, tPULSE = 30ms (Note 7) B = 100Hz to 100KHz IO1 = IFL1/10 VCC = 4.75 to 5.25V (Note 7) B = 100Hz to 100KHz VCC = 4.75 to 5.25V B = 100Hz to 100KHz VDD = 10.8 to 13.2V IO1 = IO2 = IO3 = 0 IO1 = IO2 = IO3 = 0 B = 10Hz to 10KHz (Note 7) IO = 10mA (Note 6, 7) (Note 7) Tj = 125C, 1000Hrs IO2 = IFL2/10 (Note 7) IO3 = IFL3/10 (Note 7)
0.1 30 30 40 >40 >40 >50 7 13 0.003 0.5 0.3
0.3
%/W dB dB dB
10 20
mA mA %VOUT %VOUT %VOUT
Note 1: Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data Note 2: Dropout Voltage is defined as the minimum differential voltage between V I and VO required to mantain regulation at VO. It is measured when the output voltage drops 100mV below its nominal value. Note 3: Transient response is defined with a step change in load from 10mA to IFL /2 as the time from the load step until the output voltage reaches it's minimum value. Note 4: Minimum load current is defined as the minimum current required at the output in order to maintain regulation for the output voltage. Note 5: The regulator shall withstand 100000 reverse bias discharges of the maximum output capacitance, with no degradation, when the input voltage is switched to ground in 1 s. Note 6: Temperature stability is the change in output from nominal over the operating temperature range. Note 7: Guaranteed by design, not tested in production.
APPLICATION HINTS EXTERNAL CAPACITORS The ST3L01 requires external capacitors for stability. We suggest to solder both capacitors as close as possible to the relative pins. INPUT CAPACITORS An input capacitor, whose value is at least 0.1F, is required on the VDD input; the amount of the input capacitance can be increased without limit. Any good quality tantalum or ceramic low ESR capacitor may be used at the VDD input. Any input capacitor, whose value is at least 1mF is instead required on the VCC input; the amount of this input capacitance can be increased without limit. Tantalum or aluminum electrolitic capacitor can be used at the VCC input; ceramic, low ESR capacitor are not recommended. Both capacitors must be located at a distance of not modre than 0.5" from the input pins of the device and returned to a clean analog ground. OUTPUT CAPACITOR The ST3L01 is designed specifically to work with Ceramic and Tantalum capacitors.
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The test results of the ST3L01 stability using multilayer ceramic capacitors show that a minimum value of 0.1F is needed for the three regulators. This value can be increased for even better transient response and noise performance. Surface-mountable solid tantalum capacitors offer a good combination of small physical size for the capacitance value and ESR in the range need by the ST3L01. The test results show good stability for both outputs with values of at least 0.1F. Also this capacitor value can be increased without limit for even better performance such a transient response and noise. IMPORTANT; The output capacitor must maintain its ESR in the stable region over the full operating temperature to assure stability. Also , capacitor tolerance and variation with temperature must be considered to assure that the minimum amount of capacitance is provided at all times. For this reason, when a caramic multilayer capacitor is used, the better choise for temperature coefficent is the X7R type, which holds the capacitance within 15% . The output capacitor should be located not more than 0.5" from the output pins of the device and returned to a clean analog ground.
ST3L01
TYPICAL CHARACTERISTICS (CCC=1F (tant), CDD=100nF (X7R), All C O=100nF (X7R)) Figure 1 : Output Voltage vs Temperature Figure 4 : Load Regulation vs Temperature
Figure 2 : Output Voltage vs Temperature
Figure 5 : Load Regulation vs Temperature
Figure 3 : Output Voltage vs Temperature
Figure 6 : Load Regulation vs Temperature
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ST3L01
Figure 7 : Dropout Voltage vs Temperature Figure 10 : Dropout Voltage vs Output Current
Figure 8 : Dropout Voltage vs Temperature
Figure 11 : Dropout Voltage vs Output Current
Figure 9 : Dropout Voltage vs Temperature
Figure 12 : Dropout Voltage vs Output Current
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ST3L01
Figure 13 : Current Limit vs Temperature Figure 16 : Output Voltage vs Output Current
Figure 14 : Current Limit vs Temperature
Figure 17 : Output Voltage vs Output Current
Figure 15 : Current Limit vs Temperature
Figure 18 : Output Voltage vs Output Current
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ST3L01
Figure 19 : Quiescent Current vs Temperature Figure 22 : Supply Voltage Rejection vs Frequency
Figure 20 : Quiescent Current vs Temperature
Figure 23 : Supply Voltage Rejection vs Frequency
Figure 21 : Supply Voltage Rejection vs Frequency
Figure 24 : Supply Voltage Rejection vs Output Current
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ST3L01
Figure 25 : Supply Voltage Rejection vs Output Current Figure 28 : Line Transient
VCC=4.75 to 5.25V, VDD=12V, IO1=IO2 =10mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
Figure 26 : Supply Voltage Rejection vs Output Current
Figure 29 : Line Transient
VCC=4.75 to 5.25V, VDD=12V, IO1=IO2 =10mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
Figure 27 : Supply Voltage Rejection vs Temperature
Figure 30 : Line Transient
VCC=4.75 to 5.25V, VDD=12V, IO1=IO2 =10mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
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ST3L01
Figure 31 : Line Transient Figure 34 : Load Transient
VCC=5V, V DD=10.7 to 13.2V, IO3=10mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
VCC=5V, V DD=12V, IO1=10 to 600mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
Figure 32 : Line Transient
Figure 35 : Load Transient
VCC=5V, V DD=10.7 to 13.2V, IO3=10mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
VCC=5V, V DD=12V, IO1=10 to 600mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
Figure 33 : Line Transient
Figure 36 : Load Transient
VCC=5V, V DD=10.7 to 13.2V, IO3=10mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
VCC=5V, V DD=12V, IO1=10 to 600mA, CCC=1F (tant), CDD=100nF (X7R), All CO=100nF (X7R)
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ST3L01
SPAK-7L MECHANICAL DATA
DIM. A A2 C C1 D D1 F G G1 H1 H2 H3 L L1 L2 M N V 3 8.89 0.79 0.25 6 3 9.27 8.89 10.41 7.49 9.14 1.04 0.350 0.031 0.010 6 1.02 7.87 0.63 1.27 7.62 5.59 9.52 9.14 10.67 0.365 0.350 0.410 0.295 0.360 0.041 mm. MIN. 1.78 0.03 0.25 0.25 1.27 8.13 0.79 0.040 0.310 0.025 0.050 0.3 0.220 0.375 0.360 0.420 TYP MAX. 2.03 0.13 MIN. 0.070 0.001 0.010 0.010 0.050 0.320 0.031 inch TYP. MAX. 0.080 0.005
PO13F2/A
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ST3L01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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